The present invention generally relates to a method for manufacturing a memory element. More particularly, the present invention relates to a method for making a non-volatile memory storage element.
Non-volatile memory storage elements or memory cells generally include a floating gate and a control gate. Data is stored in the memory cell by storing a predetermined amount of charge on the floating gate to define a first storage state, for example, a binary 1, and by removing substantially all charge from the floating gate to define a second storage state, for example, a binary 0.
The floating gate is substantially electrically insulated from other circuit elements. To read or change the storage state of the memory cell, a voltage is applied to the control gate to electrically couple the floating gate to a conductor such as a bit line. Generally, the floating gate is fabricated by patterning a first layer of polysilicon and the control gate is fabricated by patterning a second layer of polysilicon. Materials other than polysilicon may be used for manufacturing the floating gate and the control gate.
To maximize the number of memory cells that can be packed onto a single integrated circuit, the memory cells are made uniformly and as small as possible. To achieve this goal of small size, the floating gate and the control gate are generally fabricated with the control gate located above the floating gate, separated from the floating gate by one or more dielectric layers. Moreover, the conductor which forms the bit line is fabricated from a doped region in the semiconductor substrate itself, adjacent to the floating and control gates.
To further increase the density of storage elements, modern non-volatile memories use a virtual ground design. In a virtual ground design, the core or array of memory cells includes no metal to diffusion contacts between the semiconductor substrate and the most negative potential of the circuit. Such contacts are commonly made throughout an integrated circuit to provide electrical connection to the cells. In the virtual ground design, these electrical connections are provided through the bit line.
Moreover, to conserve space, the virtual ground memory device does not have field oxide isolation in the core or array of memory cells. Field oxide generally electrically isolates individual transistors or groups of transistors. Eliminating field oxide isolation in the core further increases the packing density of memory cells. Growth of the field oxide is generally one of the first steps in processing silicon substrates according to the LOCOS (localized oxidation of silicon) process.
In virtual ground memory devices, processing begins with deposition of a first polysilicon layer on a substrate. The first polysilicon layer will form the floating gates in the completed device. The first polysilicon layer is patterned to produce shapes approximately the width of the finished floating gates. To prevent pitting of exposed silicon surfaces during etching steps following deposition of the first polysilicon layer, a thick oxide is grown on the bit line region adjacent to the floating gate. During bit line oxidation, the exposed sides of the first polysilicon layer shapes are oxidized and oxide encroaches on the top and sides of the polysilicon. During bit line oxidation and subsequent thermal cycles, the dopant introduced into the bit line region diffuses under the floating gate. This diffusion reduces the effective gate length, L.sub.eff, of the floating gate and allows bit line to bit line leakage, disrupting the reading and storing processes in the memory device.
An important figure of merit in the design and operation of a non-volatile memory device is the coupling ratio. The coupling ratio is defined as the ratio of the capacitance between the first polysilicon layer (floating gate) and the bit line diffusion, Cdp, to the capacitance between the second polysilicon layer (control gate) and the first polysilicon layer (floating gate), Cpp. To minimize programming errors when altering the storage state of a memory element, the coupling ratio should be minimized. That is, Cdp should be decreased and Cpp should be increased.
However, the encroachment of oxide on the top of the first polysilicon layer during bit line oxidation tends to decrease Cpp, the capacitance between the polysilicon layers. Moreover, the diffusion of bit line dopant under the first polysilicon layer control gate during bit line oxidation increases Cdp, the polysilicon-to-diffusion capacitance.
Accordingly, there is a need in the art for a method for manufacturing a floating gate memory device which minimizes the coupling ratio. There is also a need in the art for a method which minimizes bit line to bit line leakage. The method of the present invention solves these problems and provides other advantages over the prior art.